While the glamour of the integrated circuit has diminished little over the nearly five decades of its existence, it has become increasingly clear in the last several years that the performance of semiconductor chips is being gated by the IC package. Once a bit of an 'ugly duckling' technology (in the early history of the IC, the package is given almost no mention), the IC package is blossoming into a swan and it is now beginning to rival the very technology that gave it birth in terms of the attention it is getting. As evidence one can point to the increasing numbers of colleges, universities and research institutes around the globe that are making a science out of what was one time somewhat of a craft. Or one can look to the explosion in packaging related patents that have been filed and issued over the course of the last ten years. The reasons are manifold but they are rooted in cost, performance and reliability. To understand how IC packaging technology got to where it is today, it is necessary to look back at the road it traveled to get here.
The IC package was born of the IC, which, though it had great potential power within, did not have the ability to easily communicate with the world beyond owing to the fine and seemingly random pitch of its contacts. The nascent electronics assembly industry did not have such assembly prowess as they enjoy today and they needed something more friendly to their needs. Thus the two companies, Fairchild Semiconductor and Texas Instruments, homes of the co-inventors of the integrated circuit, Robert Noyce and Jack Kilby respectively, each devised what was to package the delicate ICs, and they came up with two different approaches. Fairchild was first with production ICs in 1961 and ultimately provided chips in through-holemountable dual in line packages (DIP). Texas Instruments came up with the flat pack for their ICs, which was probably the first surface mount package. Both used ceramic as the insulating carrier base for the lead frames to which the chip was interconnect by miniature wires. A relatively short time later, in 1963, IBM found success with the idea of direct connection by flip mounting the chip onto ceramic circuit substrates using solder. AT&T had a somewhat similar idea, but it required attachment of a planar beam lead, which was an early precursor of tape automated bonding (TAB) assembly. Those familiar with IC packages of today will recognize 'genetic material' that remains in the various packaging technologies from the different package lineages of earlier times. With the continuing rise in I/O counts over time, the limits of the earlier solutions were reached and newer formats were developed. The most important perhaps was the pin grid array (PGA) which established the area array interconnection concept and blazed a trail for the ball grid array (BGA) package, which came into prominence in the late 1980s and early 1990s. In between those events, surface mount technology took off, and a host of peripherally leaded IC packages came into being. First on two sides and then on four, early surface mount packages included the small (or Swiss) outline package (SOP), then a shrink version, the SSOP, and finally a thin version, the TSOP. The four-sided packages were called quad leaded fine pitch or QFPs and because they were plastic PQFPs. Tape
carrier packaging (TCP), a variation of TAB, found some favor because of their fine pitch leads, which allowed for reduced area use, but it was not as efficient as area array; the assembly was very difficult and prone to solder shorts.
Chip scale packaging represented the next step in the evolution of packaging. It was fundamentally an effort to obtain the benefits of flip chip assembly (smallest form factor, highest performance, etc.) but without all of the risks and challenges, and with the benefit of standards, which is virtually impossible with flip chip. However, CSP technology has not replaced flip chip technology but has instead augmented it. The last stop in chip scale packaging is chip size, and that has been accomplished by wafer level packaging with the ICs being packaged directly on the silicon wafer.
Wafer level packaging began to take hold in the late 1990s, and today a substantial number of ICs are packaged on the wafer, mostly for lower lead count applications that do not require underfill to meet reliability requirements. That is not the end of the evolution of IC packaging, however.
Stacking of both chips within a packageand of packages on packages is now pacing IC packaging technology's evolution. This has been in response to the notion that IC packaging is now a volumetric problem. Volumetric system miniaturization and interconnection (VSMI) is required as
simply shrinking the package in the X and Y dimensions is no longer providing the size and performance demanded by today's advanced mobile products. Still, the idea of stacking of silicon chips and packages is not new and in fact it has roots in the 1980's and perhaps even earlier, but the need for such solutions was not pressing at the time. Today however, the concept of a system in package (SiP) has pressed stacked technology into service. Even these new SiP devices have precursors. Perhaps the most notable was the multichip module (MCM), which defined a path but which could not deliver cost-effectively because of the inability to get known good die (KGD).
In summary, the evolution of IC packaging technology has been a fascinating journey. It has moved from stagehand to leading actor in the theater of electronic manufacturing and may soon own the theater. Next year, 2008, marks the 50th anniversary of the invention of the IC, and while there is
no firm date to mark the invention of IC package technology, it is worth remembering the important role it has played in getting the electronics industry to where it is today. Perhaps the industry can find a way to pay homage to the IC package that made the rise of the IC possible.
Adriana Gabriela Trujillo
C.I.17863740
EES
SECC 02.
No hay comentarios:
Publicar un comentario